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cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-07141 rev. *i revised january 03, 2011 cy62137fv30 mobl ? 2-mbit (128k x 16) static ram features very high speed: 45 ns temperature ranges ? industrial: ?40 c to +85 c wide voltage range: 2.20 v?3.60 v pin compatible with cy62137cv/cv25/cv30/cv33, cy62137v, and cy62137ev30 ultra low standby power ? typical standby current: 1 ? a ? maximum standby current: 5 ? a (industrial) ultra low active power ? typical active current: 1.6 ma at f = 1 mhz (45 ns speed) easy memory expansion with ce and oe features automatic power down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power byte power down feature available in pb free 48-ball very fine ball grid array (vfbga) and 44-pin thin small outline package (tsop) ii package functional description the cy62137fv30 is a high pe rformance cmos static ram organized as 128k words by 16 bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature th at significantly reduces power consumption when addresses are not toggling. placing the device into standby mode reduces power consumption by more than 99% when deselected (ce high or both ble and bhe are high). the input a nd output pins (i/o 0 through i/o 15 ) are placed in a high impedance state in the following conditions when the device is deselected (ce high), the outputs are disabled (oe high), both the byte high enable and the byte low enable are disabled (bhe , ble high), or during an active write operation (ce low and we low). write to the device by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ) is written into the location specified on the address pins (a 0 through a 16 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 16 ). read from the device by taking chip enable (ce ) and output enable (oe ) low, while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see the ?truth table? on page 11 for a complete description of read and write modes. for best practice recommendat ions, refer to the cypress application note an1064, sram system guidelines. 128k x 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 ce we bhe a 16 a 0 a 1 a 9 a 10 ble bhe ble ce power down circuit logic block diagram [+] feedback
cy62137fv30 mobl ? document number: 001-07141 rev. *i page 2 of 16 contents product portfolio ................................................................ 3 pin configuration ............................................................... 3 maximum ratings ............................................................... 4 operating range ................................................................. 4 electrical characteristics ....... ............................................ 4 capacitance ........................................................................ 4 thermal resistance . .......................................................... 5 ac test loads and waveforms .. .............. .............. ........... 5 data retention characteristics ......................................... 6 data retention waveform .................................................. 6 switching characteristics .................................................. 7 switching waveforms ........................................................ 8 truth table ........................................................................ 11 ordering information ....................................................... 12 ordering code definition ....... ...................................... 12 package diagrams ........................................................... 13 acronyms .......................................................................... 14 document conventions ................................................... 14 units of measure ......................................................... 14 document history page ................................................... 15 sales, solutions, and legal information ........................ 16 worldwide sales and design support ......... ........... ..... 16 products ...................................................................... 16 psoc ? solutions ......................................................... 16 [+] feedback
cy62137fv30 mobl ? document number: 001-07141 rev. *i page 3 of 16 product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( ? a) f = 1mhz f = f max min typ [1] max typ [1] max typ [1] max typ [1] max CY62137FV30LL industrial 2.2 v 3.0 v 3.6 v 45 1.6 2.5 13 18 1 5 pin configuration figure 1. 48-ball vfbga pinout [2, 3] figure 2. 44-pin tsop ii [2] we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe a 7 i/o 0 bhe nc nc a 2 a 1 ble i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 26 5 4 1 d e b a c f g h a 16 nc v cc v cc v ss 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 a 6 a 7 a 4 a 3 a 2 a 1 a 0 a 14 a 15 a 8 a 9 a 10 a 11 a 12 a 13 nc oe bhe ble ce we i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 v cc v cc v ss v ss nc 10 a 16 notes 1. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c 2. nc pins are not connected on the die. 3. pins d3, h1, g2, h6 and h3 in the vfbga package are address exp ansion pins for 4 mb, 8 mb, 16 mb, and 32 mb and 64 mb respect ively.. [+] feedback
cy62137fv30 mobl ? document number: 001-07141 rev. *i page 4 of 16 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ............................... ?65 c to + 150 c ambient temperature with power applied ......................................... ?55 c to + 125 c supply voltage to ground potential ..........................................................-0.3 v to 3.9 v dc voltage applied to outputs in high z state [4, 5] ...........................................-0.3 v to 3.9 v dc input voltage [ 5] .........................................?0.3 v to 3.9 v output current into outputs (low) ............................. 20 ma static discharge voltage ......................................... > 2001 v (mil?std?883, method 3015) latch up current .................................................... > 200 ma operating range device range ambient temperature v cc [6] CY62137FV30LL industrial ?40 c to +85 c 2.2 v to 3.6 v electrical characteristics over the operating range parameter description test conditions 45 ns (industrial) unit min typ [7] max v oh output high voltage 2.2 < v cc < 2.7 i oh = ?0.1 ma 2.0 ? ? v 2.7 < v cc < 3.6 i oh = ?1.0 ma 2.4 ? ? v v ol output low voltage 2.2 < v cc < 2.7 i ol = 0.1 ma ? ? 0.4 v 2.7 < v cc < 3.6 i ol = 2.1 ma ? ? 0.4 v v ih input high voltage 2.2 < v cc < 2.7 1.8 ? v cc + 0.3 v 2.7 < v cc < 3.6 2.2 ? v cc + 0.3 v v il input low voltage 2.2 < v cc < 2.7 ?0.3 ? 0.6 v 2.7 < v cc < 3.6 ?0.3 ? 0.8 v i ix input leakage current gnd < v i < v cc ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) i out = 0 ma cmos levels ?13 18 ma f = 1 mhz ? 1.6 2.5 i sb1 [8] automatic power-down current ? cmos inputs ce > v cc ? ? 0.2 v, or (bhe and ble )> v cc ? ? 0.2 v, v in > v cc ? 0.2 v, v in < 0.2 v, f = f max (address and data only), f = 0 (oe and we ), v cc = v cc(max) ?1 5 ? a i sb2 [8] automatic power- down current ? cmos inputs ce > v cc ? 0.2 v or (bhe and ble ) > v cc ? ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v cc(max) ?1 5 ? a capacitance parameter [9] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf notes 4. v il(min) = ?2.0 v for pulse durations less than 20 ns. 5. v ih(max) =v cc +0.75 v for pulse durations less than 20 ns. 6. full device ac operation assumes a minimum of 100 ? s ramp time from 0 to v cc (min) and 200 ? s wait time after v cc stabilization 7. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c 8. chip enable (ce ) and byte enables (bhe and ble ) need to be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr specification. other inputs can be left floating 9. tested initially and after any design or proces s changes that may affect these parameters. [+] feedback
cy62137fv30 mobl ? document number: 001-07141 rev. *i page 5 of 16 thermal resistance . parameter [10] description test conditions vfbga tsop ii unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two layer printed circuit board 75 77 ? c / w ? jc thermal resistance (junction to case) 10 13 ? c / w ac test loads and waveforms figure 3. ac test loads and waveform parameters 2.5 v (2.2 v to 2.7 v) 3.0 v (2.7 v to 3.6 v) unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v note 10. tested initially and after any design or proc ess changes that may affect these parameters v cc v cc output r2 30 pf gnd 90% 10% 90% 10% rise time = 1 v / ns fall time = 1 v / ns output equivalent to: thvenin equivalent all input pulses r th r1 v including jig and scope [+] feedback
cy62137fv30 mobl ? document number: 001-07141 rev. *i page 6 of 16 data retention characteristics over the operating range parameter description conditions min typ [11] max unit v dr v cc for data retention 1.5 ? ? v i ccdr [12] data retention current v cc = 1.5 v, ce > v cc - 0.2 v, or (bhe and ble )> v cc ? ? 0.2 v v in > v cc - 0.2 v or v in < 0.2 v industrial ? ? 4 ? a t cdr [13] chip deselect to data retention time 0??ns t r [14] operation recovery time CY62137FV30LL-45 45 ? ? ns data retention waveform figure 4. data retention waveform [15] v cc(min) v cc(min) t cdr v dr > 1.5 v data retention mode t r v cc ce or bhe .ble notes 11. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c 12. chip enable (ce ) and byte enables (bhe and ble ) need to be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr specification. other inputs can be left floating. 13. tested initially and after any design or proces s changes that may affect these parameters. 14. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s or stable at v cc(min) > 100 ? s. 15. bhe .ble is the and of both bhe and ble . deselect the chip by either disabling chip enable signals or by disabling both bhe and ble . [+] feedback
cy62137fv30 mobl ? document number: 001-07141 rev. *i page 7 of 16 switching characteristics parameter [16,17] description 45 ns (industrial) unit min max read cycle t rc read cycle time 45 ? ns t aa address to data valid ? 45 ns t oha data hold from address change 10 ? ns t ace ce low to data valid ?45ns t doe oe low to data valid ?22ns t lzoe oe low to low z [18] 5?ns t hzoe oe high to high z [18, 19] ?18ns t lzce ce low to low z [19] 10 ? ns t hzce ce high to high z [18, 19] ?18ns t pu ce low to power up 0?ns t pd ce high to power down ?45ns t dbe ble /bhe low to data valid ?45ns t lzbe ble /bhe low to low z [18, 20] 5?ns t hzbe ble /bhe high to high z [18, 19] ?18ns write cycle [21] t wc write cycle time 45 ? ns t sce ce low to write end 35 ? ns t aw address setup to write end 35 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 35 ? ns t bw ble /bhe low to write end 35 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [18, 19] ?18ns t lzwe we high to low z [18] 10 ? ns notes 16. test conditions for all parameters, other than tristate paramete rs, assume signal transition time of 3 ns (1 v/ns) or less, timing reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in ?ac test loads and waveforms? on page 5 . 17. ac timing parameters are subject to byte enable signals (bhe or ble ) not switching when chip is disabled. please see application note an13842 for further clarification. 18. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 19. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedance state. 20. if both byte enables are toggled together, this value is 10 ns. 21. the internal write time of the memo ry is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals are active to initiate a write and any of these signals terminate a write by going inactive. the data input setup and hold timing are referenced to the edge of the signal that terminates the write. [+] feedback
cy62137fv30 mobl ? document number: 001-07141 rev. *i page 8 of 16 switching waveforms figure 5. read cycle 1: address transition controlled [22, 23] figure 6. read cycle 2: oe controlled [23, 24] previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t lzbe t lzce t pu high impedance i cc t hzoe t hzce t pd t hzbe t lzoe t dbe t doe impedance high i sb data out oe ce v cc supply current bhe /ble address notes 22. the device is continuously selected. oe , ce = v il , bhe and/or ble = v il . 23. we is high for read cycle. 24. address valid before or similar to ce and bhe , ble transition low. [+] feedback
cy62137fv30 mobl ? document number: 001-07141 rev. *i page 9 of 16 figure 7. write cycle 1: we controlled [25, 26, 27] figure 8. write cycle 2: ce controlled [25, 26, 27] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc t hzoe data in note 28 t bw t sce data i/o address ce we oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc t hzoe data in t bw t sa ce address we data i/o oe bhe /ble note 28 notes 25. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals are active to initiate a write and any of these signals terminate a write by going inactive. the data input setu p and hold timing are referenced to the edge of the signal that terminates the write. 26. data i/o is high impedance if oe = v ih . 27. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 28. during this period, the i/os are in output state. do not apply input signals. [+] feedback
cy62137fv30 mobl ? document number: 001-07141 rev. *i page 10 of 16 notes 29. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 30. during this period, the i/os are in output state. do not apply input signals. figure 9. write cycle 3: we controlled, oe low [29] figure 10. write cycle 4: bhe /ble controlled, oe low [29] switching waveforms (continued) data in t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 30 ce address we data i/o bhe /ble t hd t sd t sa t ha t aw t wc data in t bw t sce t pwe t hzwe t lzwe note 30 data i/o address ce we bhe /ble [+] feedback
cy62137fv30 mobl ? document number: 001-07141 rev. *i page 11 of 16 truth table ce we oe bhe ble inputs or outputs mode power hxxx [31] x [31] high z deselect or power-down standby (i sb ) x [31] x x h h high z deselect or power-down standby (i sb ) l h l l l data out (i/o 0 ?i/o 15 )read active (i cc ) lhlhldata out (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z read active (i cc ) l h l l h data out (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z read active (i cc ) l h h l l high z output disabled active (i cc ) l h h h l high z output disabled active (i cc ) l h h l h high z output disabled active (i cc ) l l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l l x h l data in (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z write active (i cc ) l l x l h data in (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z write active (i cc ) note 31. the ?x? (don?t care) state for the chip enable (ce ) and byte enables (bhe and ble ) in the truth table refer to the logic state (either high or low). intermediate voltage levels on these pins is not permitted. [+] feedback
cy62137fv30 mobl ? document number: 001-07141 rev. *i page 12 of 16 ordering code definition ordering information speed (ns) ordering code package diagram package type operating range 45 CY62137FV30LL-45bvi 51-85150 48-ball vfbga industrial CY62137FV30LL-45bvxi 48-ball vfbga (pb-free) CY62137FV30LL-45zsxi 51-85087 44-pin tsop ii (pb-free) contact your local cypress sales represen tative for availability of these parts. cy 621 3 7f v30 ll 45 xxx x company id: cy = cypress mobl sram family density = 2 mbit bus width = x16 f = 90nm technology voltage range = 3 v typical low power speed grade package type bvx: vfbga (pb-free) bvi : vfbga zsx: tsop ii (pb-free) temperature grades i = industrial [+] feedback
cy62137fv30 mobl ? document number: 001-07141 rev. *i page 13 of 16 package diagrams figure 11. 48-ball vfbga (6 x 8 x 1 mm), 51-85150 51-85150 *f [+] feedback
cy62137fv30 mobl ? document number: 001-07141 rev. *i page 14 of 16 acronyms document conventions units of measure figure 12. 44-pin tsop ii, 51-85087 package diagrams (continued) max min. dimension in mm (inch) (optional) can be located anywhere in the bottom pkg ejector mark z a z z z z x a 10.058 (0.396) 10.262 (0.404) 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) top view bottom view plane seating 18.517 (0.729) 0.800 bsc 0-5 0.400(0.016) 0.300 (0.012) 1.194 (0.047) 0.991 (0.039) 0.150 (0.0059) 0.050 (0.0020) (0.0315) 18.313 (0.721) base plane 0.10 (.004) 11.938 (0.470) pin 1 i.d. 44 1 11.735 (0.462) 10.058 (0.396) 10.262 (0.404) 22 23 51-85087-c acronym description cmos complementary metal oxide semiconductor i/o input/output sram static random access memory vfbga very fine ball grid array tsop thin small outline package symbol unit of measure c degrees celsius ? a microamperes ma milliampere mhz megahertz ns nanoseconds pf picofarads v volts ? ohms w watts [+] feedback
cy62137fv30 mobl ? document number: 001-07141 rev. *i page 15 of 16 document history page document title: cy62137fv30 mobl ? 2-mbit (128k x 16) static ram document number: 001-07141 rev. ecn no. issue date orig. of change description of change ** 449438 see ecn nxr new datasheet *a 464509 see ecn nxr changed the i sb2(typ) value from 1.0 ? a to 0.5 ? a changed the i sb2(max) value from 4 ? a to 2.5 ? a changed the i cc(typ) value from 2 ma to 1.6 ma and i cc(max) value from 2.5 ma to 2.25 ma for f=1 mhz test condition changed the i cc(typ) value from 15 ma to 13 ma and i cc(max) value from 20 ma to 18 ma for f=1 mhz test condition changed the i ccdr(typ) value from 0.7 ? a to 0.5 ? a and i ccdr(max) value from 3 ? a to 2.5 ? a *b 566724 see ecn nxr converted from preliminary to final changed the i cc(max) value from 2.25 ma to 2.5 ma for test condition f=1 mhz changed the i sb2(typ) value from 0.5 ? a to 1 ? a changed the i sb2(max) value from 2.5 ? a to 5 ? a changed the i ccdr(typ) value from 0.5 ? a to 1 ? a and i ccdr(max) value from 2.5 ? a to 4 ? a *c 869500 see ecn vkn added automotive-a and automotive-e information updated ordering information table added footnote 13 related to t ace *d 901800 see ecn vkn added footnote 9 related to i sb2 and i ccdr made footnote 14 applicable to ac parameters from t ace *e 1371124 see ecn vkn/aesa converted automotive informatio n from preliminary to final changed i ix min spec from ?1 ? a to ?4 ? a and i ix max spec from +1 ? a to +4 ? a changed i oz min spec from ?1 ? a to ?4 ? a and i oz max spec from +1 ? a to +4 ? a *f 1875374 see ecn vkn/aesa added -45bvi part in the ordering information table *g 2943752 06/03/2010 vkn added contents added footnote related to chip enable and byte enables in truth table updated package diagrams updated links in sales, solutions, and legal information *h 3055031 10/12/10 rame added acronyms and units of measure table converted all table notes into footnotes. updated electrical characteristics , switching characteristics table, and data retention characteristics table updated package diagrams from 51-85150 *e to *f changed i sb1 /i sb2 /i ccdr test conditions to reflect byte power down feature *i 3123998 01/03/2011 rame separated automoti ve and industrial parts from datasheet removed automotive info [+] feedback
cy62137fv30 mobl ? ? cypress semiconductor corporation, 2006-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reas onably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document number: 001-07141 rev. *i revised january 03, 2011 page 16 of 16 mobl is a registered trademark and more battery life is a trademark of cypress semiconductor. all product and company names men tioned in this document are the trademarks of their respective holders . sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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